1. Field of the Invention
The present invention relates to integrated circuit non-volatile memories. More particularly, the present invention relates to non-volatile memory arrays having source-side column select architectures.
2. The Prior Art
Background leakage and gate-induced-drain-leakage (GIDL) stress is a serious issue in hot-carrier-injection programming schemes for flash memory devices and flash-based FPGA devices.
Prior-art designs employ a column select transistor at the drain side of the memory transistor. The column-select device is usually a high-voltage transistor which requires large-area well boundaries.
FIGS. 1A and 1B are simplified schematic diagrams illustrating representative prior-art flash memory programming techniques. In FIG. 1A, a drain-side column-select transistor is coupled to a flash memory transistor. The source side of the flash memory transistor is coupled to ground through a source bias resistor. To program the flash memory transistor, the gate of the drain-side column-select transistor is biased at about +8.5V, the gate of the memory transistor is biased at about +8.5V, and 5V is applied to the drain of the drain-side column-select transistor. As will be appreciated by persons of ordinary skill in the art, a sector-based column select scheme is usually employed.
In FIG. 1B, a drain-side column-select transistor is coupled to a flash memory transistor. The source side of the flash memory transistor is coupled to ground through a source-side select transistor. The column-select scheme is also sector based in this arrangement. To program the flash memory transistor, the gate of the drain-side column-select transistor is biased at about +0 v to +10V, the gate of the memory transistor is biased at about −20V to +20V, the gate of the source-select transistor is biased at about 0V to +15V, and 0V to +10V is applied to the drain of the drain-side column-select transistor.
The arrangements of FIGS. 1A and 1B have several drawbacks. The drain-side column select transistor must be a high-voltage transistor or a floating gate access transistor. This requires well spacing design rules for well boundaries between non-volatile memory wells to high voltage logic wells.